In wireless communication systems, quadrature amplitude modulation is used for transmitting the radio frequency (RF) signal. In most of the wireless systems, the information bearing base-band signal is in a digital format. In an RF transceiver, to transmit the base-band digital signal, it is converted to analog form by using a digital-to-analog (DAC) converter. This analog signal is up-converted by modulating a high frequency carrier to make it suitable for transmission. On the receiver side, the received high frequency signal is demodulated and converted to digital format by analog-to-digital (ADC) converter. The DAC and ADC are the power and silicon-area consuming blocks in a typical transceiver. The complex design of these blocks is very time consuming, resulting in a high design cost. Design complexity, power consumption and silicon-area are the important factors in mobile wireless applications for determining the cost.
FIG. 1 is a block diagram of a typical transmitter used in a radio-frequency (RF) transceiver chip of wireless communication systems. Referring to FIG. 1, the information bearing base-band signal is a digital signal having ‘I’ and ‘Q’ components, which are referred to herein as I-data and Q-data, respectively. ‘I’ and ‘Q’ are N-bit wide parallel data (where N can be in the range of 1 to 20), that are generated by a digital baseband signal processor. In the RF transceiver chip, the I-data and Q-data of the base-band digital signal are converted to analog for by using digital-to-analog (DAC) converters 101 and 102, respectively. The outputs of DACs 101 and 102 are filtered with filters 103 and 104, respectively, to remove out-of-band components introduced by DACs 101 and 102. Thereafter, the analog signals output from I filter 100 and Q filter 104 are fed into variable gain amplifiers (VGAs) 105 and 106, respectively, and then up-converted to a high frequency suitable for transmission by modulating a carrier frequency.
Many of the systems modulate the carrier as quadrature amplitude modulation (QAM) using a single-side band (SSB) mixer that is an analog RF block. In FIG. 1, a pair of mixers 107 and 108 is used. Mixer 107 up-converts the analog I-data, which has been filtered and amplified, using an I-clock output from divider 109. Mixer 108 up-converts the analog Q-data, which has been filtered and amplified, using a Q-clock output from divider 109. Divider 109 generates I-clock and Q-clock from a clock signal from oscillator 110 by dividing the frequency by two. Thus, generated I and Q clocks have half the frequency of the oscillator and they differ in phase by 90 degrees. The outputs of mixers 107 and 108 are combined using adder 111 that operates as a combiner to provide the SSB output, The output of adder 111 is amplified by RF driver amplifier (RF PA) 112. In low power systems such as UWB, Zigbee, RF IDs, usually, RF PA 112 is the final stage providing RF output for transmission, However, in the cellular and WLAN systems, the RF PA 112 act as pre-driver and provides output to an external power amplifier. A bandpass filter (BPF) 113 filters the output of amplifier 112. The signal output from BPF 113 is then transmitted using antenna 114.
FIG. 2 is a block diagram of a typical receiver used in a radio-frequency (RF) transceiver chip of wireless communication systems. In the receive mode, the signal picked up by antenna 241 is passed through a band pass filter (BPF) 201 for selecting the desired range of frequencies in which the transmitted signal is expected. After filtering by BPF 201, the signal is amplified by a low noise amplifier (LNA) 202. Thereafter, the signal is demodulated by I mixer 203 and Q mixer 204 of I/Q demodulator 240 to provide I and Q base-band signals in analog format. I mixer 203 and Q mixer 204 are driven by “in-phase” (I) clock 221 and ‘quadrature’ (Q) clock 222 generated using oscillator 230 and divider 231 as described above for the transmit signal. The I and Q signals are filtered by I filter 205 and Q filter 206, respectively. The demodulated analog baseband signals are amplified by variable gain amplifiers (VGAs) 20, and 208 to bring it to suitable amplitude level as required for ADCs 209 and 210. ADCs 209 and 210 convert I and Q analog signal into digital format. The digital I and Q signals are passed on to the base-band processor for further processing of the received data.
As can be observed from the FIGS. 1 and 2, that the ADCs and DACs are used in the communication systems. These blocks are difficult to design and increase the complexity of the transceiver.